Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally >1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “optics;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
As illumination systems have evolved from producing conventional to annular, and on to quadrupole and more complicated illumination configurations, the control parameters have concurrently become more numerous. In a conventional illumination pattern, a circular area including the optical axis is illuminated, the only adjustment to the pattern being to alter the outer radius (σr). Annular illumination requires the definition of an inner radius (σc) in order to define the illuminated ring. For multipole patterns, the number of parameters which can be controlled continues to increase. For example, in a quadrupole illumination configuration, in addition to the two radii, a pole angle α defines the angle subtended by each pole between the selected inner and outer radii.
Concurrently, mask technology has been evolving as well. Binary intensity masks have given way to phase-shifted masks and other advanced designs. While a binary mask simply transmits, reflects or blocks imaging radiation at a given point, a phase-shifted mask may attenuate some radiation or it may transmit or reflect the light after imparting a phase shift, or both. Phase-shifted masks have been used in order to image features which are on the order of the imaging radiation's wavelength or smaller, since diffraction effects at these resolutions can cause poor contrast and end-of-line errors, among other problems.
The various types of illumination configurations can be used to provide improvements in resolution, depth of focus, contrast and other characteristics of the printed image. However, each illumination type has certain tradeoffs. For example, improved contrast may come at the expense of depth of focus; each type of mask has a performance which is dependent on the pattern to be imaged as well.
Conventionally, in order to select the optimum illumination mode for a given pattern to be imaged onto a wafer, a series of test wafers has been exposed and compared on a hit-or-miss basis. As noted above, modern illumination systems have ever increasing numbers of variables which can be manipulated. As the various permutations of variable settings increase, the cost of trial and error optimization of illumination configurations becomes very large and quantitative methods of selecting illumination configurations are needed. Furthermore, although an illumination optimization method has been proposed in which only a small area, such as a particular cell in a memory, is optimized, it is desirable to develop a method of optimizing illumination for a full-chip layer.